The present invention relates in general to memory devices, and in particular, to interleaved memories readable in a synchronous mode by successive locations with a sequential type of access that is commonly referred to as burst mode, and to standard memories readable in a random access asynchronous mode with fast access times.
In a standard memory, a read cycle is defined from a request of data initiated by the input of a new address, to the final output of the bits stored in the addressed location (byte, word, etc.). Internally, the reading process evolves through several steps. These steps include the acquisition of the new address, its decoding, the generation of synchronizing pulses for the sensing circuits, and the output of the read data, etc. The fundamental steps of a read cycle and the typical control signals that are used for managing it are depicted in FIG. 1.
The address transition detection (ATD) signal recognizes a change of the address input by the external circuitry, and therefore a new access request, and initiates a new read cycle. After enabling the sense amplifiers by the signal SAenable, an equalization of the sensing circuitry takes place. At the end of which, as timed by the signal EQZ, the effective reading of the memory cells takes place. Finally, after a certain interval of time that may vary from device to device, and by way of a signal SAlatch, the recording of the read data into the latches in cascade to the sense amplifiers takes place. This is from where the read word may be transferred to the output buffers.
In memory devices designed for a synchronous read mode with a sequential type (burst) of access, the reading process exploits the fact that the reading takes place by successive locations, that is the subsequent memory location to be read, and therefore its address is predictable from the address of the location being currently read. A subgroup of these sequential (burst) synchronous read mode memories is represented by the so-called interleaved memories. A burst access interleaved memory is described in U.S. Pat. No. 5,559,990.
In this type of memory, the cell array is divided in two semi-arrays or banks, each having its own read circuitry. The read streams of the two banks are thereafter superimposed according to one of the most commonly followed approaches, i.e., outphased from each other. On one of the two banks or semi-arrays the steps of evaluation and transfer of the data to the output are being performed, and on the other bank or semi-array (known as the next location to be addressed) a new read cycle may be started without waiting for the conclusion of the current read cycle that involves the first semi-array.
In interleaved memories, a basic scheme of which is depicted in FIG. 2, the array is divided in two independent banks or semi-arrays, EVEN and ODD, each having its own independent read path. Typically, there are two counters, one for each bank, containing the address of the currently pointed memory location. In case of simultaneous reading processes evolving respectively on the two semi-arrays, the least significant bit of the address (A0) supports the multiplexing between the EVEN and the ODD banks. If A0=0, the data coming from the EVEN semi-array will be made available at the output. If A0=1, the data coming from the ODD semi-array will be made available at the output.
As it is commonly known, the reading of the two semi-arrays is carried out according to one of two different approaches: 1) a simultaneous reading and multiplexing of the outputs, and 2) time outphased readings.
According to the first approach, the readings are simultaneous on the two banks. The data read are stored in respective output registers and made available to the outside world in synchronization with an external clock signal. According to the second approach, the readings on the two semi-arrays have an alternate and interleaved evolution on a time base.
The first approach, though offering a simpler hardware implementation, limits the minimization of the start times of synchronous read cycles. For a better comprehension, it is necessary to consider the basic steps that are performed when passing from an asynchronous read mode to a synchronous read mode. With reference to the scheme of FIG. 2, and assuming that the start of which is with the reading from an address X, the latter will be loaded on the EVEN bank counter and on the ODD bank counter, less the least significant bit (A0) of the address. The two counters will point to the same location X of the respective bank or semi-array.
If A0=0, the first read data is relative to the address X of the bank EVEN and the successive read data is the data X of the bank ODD. If A0=1, the first read data is relative to the address X of the bank ODD and the successively read data is relative to the X+1 address of the bank EVEN.
In the first case, it is sufficient to perform a simultaneous reading of the two banks and multiplex the outputs. In the second instance, it is necessary to increment the counter before starting the reading on the bank EVEN.
Usually, known synchronous memory devices do not make any initial increment and wait for the successive cycle for incrementing both counters, and therefore read the location X+1 of the banks EVEN and ODD. This makes the times of the first read cycle and of the second sequential read cycle at best equal to the asynchronous read mode time of the memory.
In general, it may be stated that the efficient management of the read processes has a direct influence on the performance of the memory device. Many read-path architectures have been proposed. Known read-path architectures have generally been conceived for responding efficiently to either one or the other of the two modes of operation: asynchronous or synchronous.
If a memory device is designed to be read in the asynchronous mode, it will generally be provided with a rather simple control circuitry for the read data streams, utilizing adaptive structures such as dummy wordlines and dummy sense amplifiers, while leaving the reading circuitry free to evolve as fast as possible to achieve the shortest asynchronous access delays.
In contrast, in memory devices designed to function in a burst access mode or in a synchronous read mode, the possibility of making available in output a certain number of words read and stored in advance, permits, after a first asynchronous access, as long as it may be, a series of extremely fast read cycles. In this case though, the control logic must intervene extensively to manage the sense amplifiers which should not be left to evolve freely but be enabled, equalized and read at precise instants established by the control system. Prior European Patent Application No. EP-98830801, filed on Dec. 30, 1998, and Italian Patent Application No. MI99A00248, filed on Nov. 26, 1999, describe burst-mode EPROM devices with the above characteristics.
A multipurpose memory device that can be used in a broader range of applications, whether requiring the reading of data from the memory in asynchronous mode with random access (as in a standard memory) or the reading of data from the memory in synchronous mode with sequential or burst type access, is disclosed in European Patent Application No. EP-00830068.3, the entire contents of which are incorporated herein by reference, and which is assigned to the assignee of the present invention.
This device is capable of recognizing the mode of access and the reading that is currently required by the microprocessor and the self-conditioning of its internal control circuitry as a function of such a recognition. This is done to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time of data compared to those which, for the same fabrication technology and state of the art design, may be attained with memory devices specifically designed for either one or the other mode of operation, that is, random asynchronous access and burst interleaved synchronous access.
Depending on the protocol of the control signals, CEn, OEn and ALE, it is possible to manage the memory device both in synchronous mode as well as in asynchronous mode. In particular, if ALE=1 always, the memory device functions as an asynchronous memory. If ALE is a pulsed signal (FIG. 3), after the first asynchronous reading OEn behaves as a true clock signal, so a new data is output at each rising edge thereof (synchronous readings).
The above mentioned approach, and several other similar approaches, are burdened by the following drawbacks. One drawback is the presence of an additional pin for the additional control signal ALE, which is necessary to catch all external addresses in case of asynchronous access. Another drawback is the incompatibility with standard memory devices in which this additional pin is not expected. A third drawback is the specific protocol that uses the signal OEn as a clock signal for synchronous reading. Yet another drawback is the need of the user to redesign the software and hardware of the system.
An object of the present invention is to provide a multipurpose memory device that has an interlaced architecture and function, and is fully compatible with standard memory devices.
The control logic of the memory device is capable of recognizing the two following situations: a current address consecutive to the previous one, and a current address not consecutive to the previous one.
In the first case the data is immediately output and the memory device functions in a synchronous mode, where the synchronization is not established by an external clock but by the change of address. In contrast, the second case a new asynchronous reading cycle is started.
In the architecture of the present invention, there are two totally independent and uncorrelated reading paths for the data stored in the two banks or semi-arrays of an interlaced memory device (EVEN and ODD). The memory functions in two different modes, synchronous and asynchronous, using a circuit for detecting address transitions that act as a synchronous clock of the system, which lets the control circuit of the memory device recognize the required access mode by enabling the comparison of the currently input address with the previous one.
Each time that an address not consecutive to the previous one is input, the device internally starts two outphased and independent read cycles relative to the current address and to the immediately successive address. This is done in order to be ready to carry out an eventual possible successive synchronous reading cycle. The device is capable of switching to a synchronous read mode whenever consecutive addresses are input, thus halving the access time.
The memory device of the invention is able to recognize internally whether the currently input address is consecutive to the previous address or not, and in the negative case it produces a signal UPDATE that is used to update the pointers to the memory cells, EVEN_COUNTER and ODD_COUNTER.
The counters of the two banks are incremented separately in order to outphase the readings on the two banks starting from the first read cycle. The two distinct read processes, the one on the pointed bank and the other on the bank not being pointed to, respectively, are congruent with each other and are alternated and interleaved in time.
According to a preferred embodiment of the invention, the memory device comprises a buffer for loading data to be output, and is provided with means that precharge the output node to an intermediate voltage between the voltages corresponding to the two possible logic states of a data, thus reducing noise and optimizing the transfer time.